Read-only memories (ROMs) are non-volatile memory devices that are programmed once. ROMs are high-density storage elements designed to accept an address and to return data associated with that address. As shown in FIG. 1, a conventional ROM 2 consists of a two-dimensional array of storage elements or memory cells 3, wordline WL (row) decoder circuitry 4 and data or bitline BL (column) decoders 6 and sense amplifiers 8. Wordline decoder circuitry 4, positioned on one side of the array, is designed to activate one row of storage cells at a time based on the input address provided to ROM 2.
Each memory cell 3 is programmed to store one of the two logic states during the fabrication of the cell by connecting the gate of the transistor to either the source of the transistor (e.g. if the cell is to store a logic “1”) or to the wordline WL that corresponds with the cell if the cell is to store a second logic state (e.g. logic “0”). The information stored within the two-dimensional array of memory cells 3 traverses the bitlines (in column formation) to the sense amplifiers 8, where the analog voltages from the bitlines are converted to a digital signal. Bitline data decoders 6 relay the requested data to external circuitry (not shown) based on the other part of the input address. One current example of ROMs being used today, is in lookup tables for complex calculations in micro-processor units (e.g. fast division or transcendental functions).
Typically, the data contents of a ROM are determined at the time of creation and are static. However, there are exceptions in which the contents of a ROM can be modified at a later point in time. One example of such an arrangement is disclosed in William D. Brown and Joe E. Brewer, Nonvolatile Semiconductor Memory Technology IEEE Press, 1st edition, 1998. Even so, the desireability of ROMs over other non-volatile memories (e.g. flash EEPROMs) is related to the fact that while non-volatile memory can be altered after manufacturing, this capability comes at the cost of decreased density and increased manufacturing complexity. If an application truly requires a static data set, a ROM will cost less and operate at higher speed.
Accordingly, various types of ROM memory cells are in widespread use in the electronics industry. The following are a few examples of conventionally utilized ROM memory cells.
NOR ROM Cell
FIG. 2A illustrates the structure of a NOR ROM memory cell 10 that uses one transistor to represent one bit. The combination 11 of a resistive device connected to a fixed potential, provides a default value for the memory cells. The wordlines WL0 and WL1 run along rows of cells. Also, since wordlines are built using polysilicon (a high resistive material), a conductor layer is typically placed on top of the polisilicon and electrically connected to the polisilicon periodically. This allows the metal to act as a low resistance backup path and results in a low resistance wordline. As is conventionally known, a one or zero in a memory cell is represented through the presence or absence of the cell transistor or connection to the bitline. Some ROMs are built such that the connection to the bitlines is made in the highest layer of metal, to facilitating the “writing” of the ROM data contents at a later date. Bitlines are either actively pre-charged between reads or are connected to a weak pull-up device. FIG. 2A shows two NOR ROM cells connected to a bitline BL along with a pre-charge device 11. In this case, if either wordline WL0 or WL1 turns on, the bitline BL would be pulled low.
The number of cells attached to a bitline depends on the design considerations, namely the desired density versus speed. Typical values range from 32 to 256 cells in a column. A read operation is conducted by first decoding the address to activate one wordline. The wordline turns the access transistors “on”, which may or may not exist. Depending on the presence or absence of the transistor within the cell, the associated bitline will or will not be pulled low from a pre-charged level. The voltage swing on the bitlines is sensed by a sense amplifier and the data at the columns is multiplexed out to produce the output of the ROM. The wordline is turned “off” and the bitlines are then pre-charged in preparation for the next read.
NAND ROM Cell
FIG. 2B illustrates a conventional NAND ROM memory cell 12 where memory cells are connected in series within a column to form the bitline BL. This is in contrast to the NOR ROM 10 of FIG. 2A, where memory cells within a column are connected to the bitline in parallel. During normal operation, all the wordlines WL0 and WL1 are “on”, with the exception of the addressed wordline, which is turned “off”. If a bypass connection (from the source to drain of the transistor) exists, “zero” is stored in the memory cell. In such a case, the act of turning “off” the cell transistor has no effect on the state of the bitline BL. On the other hand, if a bypass connection does not exist, the transistor will turn off, the bitline BL will charge high and a value of “one” will be read. The NAND ROM 12 of FIG. 2B has its cells in series and no bypass connection exists in either cell. Therefore, if either wordline WL0 or WL1 was to turn “off” (it should be noted that all wordlines in a NAND rom are by default “on”) the bitline BL would charge high. Due to the series connection between cells, a large amount of resistance can be seen on bitline BL, thus limiting the speed of operation for this NAND ROM cell architecture.
Multi-Valued ROM Cell
FIG. 2C illustrates a multi-valued ROM memory cell 14 which operates in much the same way as the NOR ROM 10 of FIG. 2A, except that multi-valued cells store information through the modification of the storage transistor (e.g. by changing the width or length of the transistor). The resulting variation in sourcing current can be sensed and converted to a binary value. Specifically, in FIG. 2C, the relative widths of the transistor are represented above the transistor (i.e. as “1”, “2”, “3” or “4”). Shown are four variations on the size of the transistor, which effect the drive strength. The underlying cell configuration is that of a NOR network, where the cells are connected to the bitline BL in parallel.
Non-Volatile Memories
Non-volatile memories allow the contents of the memory to be modified. For example, Flash EEPROMs, consist of many different types: floating gate, charge-trapping, ferro-electric and magnetic devices. In principle, floating gate and charge-trapping non-volatile memories work by altering the threshold of a transistor though the injection of charge into a region between the transistor gate and the channel. This charge can be stored in a conducting layer (floating gate) or a non-conduction layer (charge trapping). Depending on the technique used, densities can approach those of DRAM. However, non-volatile memories typically lag behind by one or two generations as documented in William D. Brown and Joe E. Brewer. Nonvolatile Semiconductor Memory Technology, IEEE Press, 1st edition, 1998.
Further, by finely controlling the amount of charge injected into the floating gate, more than two levels can be stored as discussed in C. Bleiker and H. Melchior. A four-state eeprom using floating-gate memory cells. IEEE Journal of Solid-State Circuits, 22(3):460–3, June 1987. Specifically, both 4-level and 16-level EEPROMs have been reported (see D. L. Kencke, R. Richart, Shyam Garg, and S. K. Banerjee. A multilevel approach toward quadrupling the density of flash memory. IEEE Electron Device Letters, 19(3):86–8, March 1998). EEPROMs benefit from their re-programmability and that they can hold there charge for over ten years. However, for those applications that do not require the memory to be modified, ROMs hold a clear advantage in that they require no modification to the integrated circuit manufacturing process and they typically have a smaller cell size.
Multiple Bitline ROM Cell
FIG. 2D illustrates an example of a multiple adjacent bitline ROM memory cell 16 designed according to a relatively new technique which uses multiple bitlines BL1, BL2, BL3 and BL4 in a ROM as disclosed in U.S. Pat. No. 6,002,607 to Dvir. Dvir describes a method by which the drain of a transistor in a ROM cell can connect to one of many adjacent bitlines BL1, BL2, BL3 and BL4 which allows a single transistor to store multiple bits. Also presented is a method by which x bits can be stored using x+1 bitlines and x/2 transistors. This reference states that for a 2-bit cell, that the bitline capacitance is reduced by approximately 75%. This reduction is due the to reduced number of transistors connected to each bitline BL1, BL2, BL3 and BL4. However, such a large reduction would only appear possible if the parasitic capacitance of the bitlines is ignored.
Multiple Transistor Cell
FIG. 2E shows an example of how two transistors can be used to connect to a combination of two of the bitlines BL1, BL2, BL3, BL4 and BL5 (or one or no bitlines). In the case of multiple bitlines BL1, BL2, BL3, BL4 and BL5, it is possible to use multiple transistors to connect to them. This allows for multiple bits to be represented by two or more transistors configured together in this way. The theoretical number of bits that can be represented is the “log base two” of the total number of combinations of connections between the transistors and the bitlines BL1, BL2, BL3, BL4 and BL5.
Storage density, or simply density, is defined to be the amount of storage divided by the area required to implement the storage. For a ROM, the area includes decoders, sense amplifiers and an external interface (periphery circuitry) along with the storage elements. Generally, the periphery area is ignored and cell density is calculated as the number of bits stored in the cell divided by the area of the cell. While the density of the above-noted ROM devices have been sufficient for past and present computing needs, as the devices that utilize ROMs get smaller, cheaper and faster, there is a continuing need for ROMs that are faster, consume less power, and require less silicon to implement and manufacture.